Drawing the SchematicĬreate a new Schematic source (“counter”), and draw the schematic. If you would prefer to load up the finished project, then you can find it in the downloads for this book (see Chapter 2) in Project Folder ch03_counter. Give it the name “counter.” You should find that when you run the New Project Wizard, this time it remembers all the project settings from the last project, which means that you can accept the default settings and they will be correct for your board. Let’s build that counter using the schematics editor in a new project.Īs you did with the “selector” example, start by creating a new project. If only so you can find in the timing report or gates after synthesis.In Chapter 2 we saw how a counter could be built using four D flip-flops. It is better to have a defined signal in your system. Thus you have to change the signal names somewhere. The 'o' signals from one module will be the 'i' of another. Last: I would not use all the 'i's and 'o's. Give the counter enable signal a decent name: 'count_enable' not 'signal'. Your reset condition looks flawed to me but you have to solve that. The total then becomes: module contadorAscMax What you don't mention, but what I see from your code you also have an enable (iCE) and an unused output oQ. This then leads to: always or posedge reset) I want to have a counter which goes from 1111 to 0000 when a signal is present, else I want it to count up. The trick with code like this, is to make the definition using 'programming' language. Although that is a good idea for complex logic, for a simple 4 bit counter it is a bit over the top.įor solving your problem you are close. You have split the code in a register and combinatorial section. Wait 100 ns for global reset to finish I am very new to verilog so my code probable doesn't make much sense to a hardware guy, since I am a software engineer so sorry if there are some rookie mistakes here.Īs for the testbench, here is what I have: `timescale 1ns / 1ps Here's what I've been able to come up with so far: module contadorAscMaxīut it just won't wait for the signal. So I have my counter in verilog which is 4 bits and I want it to stay on max value, 1111, until I give it a signal to start counting from 0000 again.
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